Higher-order modulators, e.g., third-order or higher modulators, such as sigma-delta modulators, pulse-width modulators, and the like require some mechanism to reset or control the modulator when the modulator is overdriven to prevent unstable conditions that can produce undesirable transients in the output signal.
One conventional device to control a higher-order modulator from being overdriven relies on resetting the state variable(s) (e.g., any quantity that indicates the current state of the modulator, such as the output voltage at each integrator stage, or the charge on the integrating or switched capacitor) to zero, or a stable point, when the modulator enters an unstable condition (e.g., overdriven or overloaded). The device typically employs a switched capacitor network at the input to the integrator stage which includes an operational amplifier (op amp). An integrating capacitor is typically coupled in the feedback loop between the output and input of the op amp. The feedback path of the integrating capacitor also typically includes a reset switch. The reset switch is usually coupled to a detection device that monitors the occurrence of an unstable condition. When the unstable condition is detected, the reset switch is closed which resets to zero the integrating capacitor of the integrator stage. This resets the state variable(s) to a zero state, e.g., a stable state or condition. See, for example U.S. Pat. No. 5,021,244, incorporated herein by reference. However, resetting the state variable(s) of the integrator stage to zero results in large transients in the output signal.
Another conventional device and method for resetting the state variable(s) of a higher-order modulator, such as a delta-sigma modulator, is disclosed in U.S. Pat. No. 6,061,009 (the '009 patent), incorporated by reference herein. The '009 patent overcomes the problems associated with resetting the integrating capacitor of integrating stage to zero by utilizing reset circuitry connected in series with the reset switch in the feedback loop of the integrating capacitor. The reset circuitry introduces a “lossy” circuit (impedance), e.g., a second capacitor, in the reset/feedback loop of the integrator. Instead of instantaneously short circuiting the connection across the integrating capacitor with the closure of the reset switch, the device as disclosed in the '009 patent “adds” an impedance in parallel with the integrating capacitance in the reset feedback loop when an overdriven condition is detected. The added impedance, e.g., capacitor, receives leakage from the integrating capacitance to adjust the state variable(s) of the integrator stage to allow the integrator stage to operate as a “lossy integrator” when the modulator is overdriven. When the overdriven condition is no longer present, the reset switch is opened and the lossy circuit is taken out of the feedback loop. However, the apparatus as disclosed in the '009 patent utilizes significant chip space because two separate capacitors must be utilized: one for the integrating capacitor and another for the “lossy circuit”. When the modulator is not overdriven, the capacity of and the area utilized by the lossy circuit is wasted.